The present invention relates to improved data processing method, and more specifically, to method for managing data flow within a multi-level memory hierarchy of a computer system and preventing trailing edge latency for fetch data forwarded from a shared data/control interface.
In a computer system, the processor (CPU) executes instructions of a program. Typically, execution of instructions involves fetching (e.g., loading) and reading data into registers from memory (e.g., a cache), performing operations on the data, and storing and writing the results of the operations to memory, for example. Sometimes there may be upstream interface bottlenecks that increase target fetch data latency within a computer system. These upstream interface bottlenecks are caused by data stream interruptions and/or smaller upstream interface bandwidth which affect latency over the final high bandwidth uninterruptible data interface (e.g., L3 cache to L2 cache interface). A current method involves accumulating data in a buffer until all data is received and then returning the entire line over the L3 to L2 interface with no gaps. This method directly affects the latency of the L2 cache receipt of the target data. Another method allows gaps on the final L3 to L2 interface thereby solving the latency problem for the target data, however, it fails to eliminate a trailing edge penalty or prevent other fetches from being delayed due to the unavailability of the data bus.